What is an ASIC tape-out? First of all, the size of the database that the manufacturer of a chip receives was big. There was no way to send it via the internet since that would take too long. I remember the year 2000, a tape was the medium to store the database. This tape shipped to the destination country, usually Taiwan, to the foundry. TSMC and UMC, both Taiwanese, own more than 50% of the market for foundry business. In 2019. Some semiconductor companies still have their own manufacturing, Intel for example. But most, like AMD, have split off their manufacturing in a separate entity. So, how much does it cost to tape-out an ASIC?
First of all, I talk foundries here. Most semiconductor companies are fabless (meaning: no fabrication of the chips itself). A chip design project buys IP licenses for analog and/or digital IP. Or they design part or the whole chip themselves. Digital designers use a language to describe their digital circuit. It has a software syntax but it describes hardware. The premise is that the HDL is independent of the technology that implements the circuit. If you target an FPGA or an ASIC technology, in principle, the same code can be used. A synthesis tool needs two inputs: the HDL design and a library of cells. The cells are specific for the technology used. A TSMC 16nm process has several libraries. One for highest performance, one for smallest area and one for low power as well.
This is the traditional trade-off the chip designer must make:
- Maximum frequency.
- Smallest area.
- Lowest power consumption: static as well as dynamic.
So, the higher your frequency, the more dynamic consumption for the same technology node. Now, the library contains the basic logic gates, boolean algebra says you need AND, OR and NOT to implement any boolean equation. Furthermore, there will be flipflops as well, they store one bit value based on a clock frequency. Also other libraries are available, for memories for example, but this leads us too far from the question.
The deal with the foundry is clear, you need to deliver a chip database. Hence, the layout engineers create a floorplan. Then they place and route all the technology cells. So, the design delivered is only for this foundry and for this cell library of the foundry. If I target TSMC 16nm, I cannot use the same layout for a UMC 16nm process. Depending on the volume of chips you need and the technology node, you will get a price from the foundry to take the layout (from the ASIC tape-out database) and make a first batch of chips, usually a few wafers, covering several process corners. Finally, there are several other factors that influence the cost, like a hot lot, super hot lot, … How fast do you want it?
The number please, James
First of all, the price for a tape-out in a certain technology is a secret. Foundries don’t want you to know. Because the pricing is really customer based. Anyway, today there are two companies that have a 7nm node in production. Samsung and TSMC . The numbers that go around estimate the cost of building a 7nm fab at 14 billion USD. Global Foundries, for example, gave up on 7nm. A tape-out for a big semiconductor company costs, estimated, 250 to 500 million USD (*) for a complex system-on-chip and in 7nm technology. This is the cost from design phase to silicon production. However, small startups beat the big companies to the market regularly. They are faster, use far less resources and use a limited budget. The minimum budget would be 50 million USD, which is a factor 10 compared to the giants. Older tech nodes, 16nm , 22nm and higher are much cheaper from a foundry perspective. If we only look at the mask making for a first tape-out and samples without design cost, then it would be 500.000 USD to 1 maybe 2 million USD for technologies from 40nm downto 16nm.
Interesting article: TSMC 7nm and 5nm.
(*) The problem is what do you need for your silicon? Do you include a respin (full mask set) or metal patch only in the budget? Validation, application software, certification? It is not easy to compare budgets if you don’t know what exactly is included. The conclusion is that a system on chip costs tens to hundreds of millions of USD.
Interesting as well: what is the difference between FPGA, ASIC and PSoC?