- First of all, clock and reset strategy: gating, async/sync reset, synchronization (metastability), … .
- Then, mathematical operators, add, substract, multiply, divide and the HW inferred. Relationship between area, power and speed. Signed versus unsigned.
- Also, inferred versus instanced.
- Maybe, single port/dual port synchronous memory access.
- Furthermore, pipelining to meet timing.
- Finally, basics of on-chip bus protocols, like amba (APB, AHB, AXI). Master, slave, register map. arbitration, DMA.
Quora space : HW accelerators eating AI