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Why we are not applying DFT (Design for testability) at time of RTL Design in the ASIC design flow?

Lint check tools have a lot of rule checks to make sure the code that you write and simulate, is in line with the basic requirements for DFT. Hence all registers need a reset. There are controls for bypass of reset and clocks for the testmode clock. These lint checks improve the quality of the design going to the synthesis guys (and DFT). That saves a lot of back and forth. Every time something returns from a later stage in the project, the changes require validation again. For basic DFT, the scan patterns, you need scan chains. In RTL, your registers are in a clocked process (and reset of course). This is the functional path from data output of the previous flipflop to the data input of the next flipflop.

EDA tools: synthesis

The synthesis tool translates this to the tech library cells for registers. It is after synthesis that the concept of registers, the tech dependent cell appears. It has clock, reset and data inputs and data output, simply put. But it also has test related pins. In functional code the chain of flipflops has no meaning. After synthesis, the real cell with the test IO is available. It is easy to connect the registers in a chain. This is called “scan chain stitching”.

The DFT engineer can change the number of flops per chain, limit the number of chains or even put two chains in different clock domains (and these could be in a totally different module in the RTL hierarchy) together.

Conclusion: linting can help to make sure some essential rules are met in RTL but the real test implementation, like the chain stitching needs to be done in the netlist, it does not make sense to do this in RTL.

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