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What do you choose between VHDL and Verilog for VLSI design?

VHDL or verilog? That is the question. VLSI design uses a HDL, a hardware description language. So, the trend today, is towards systemverilog for everything. Because we can use systemverilog for both testbench and RTL code. It removes the need for mixed language licenses. As always, legacy code bites us in that special place. Today, we buy mixed language licenses because of the past.

Even though, in theory, systemverilog has everything to simulate and design. ASIC EDA tools are expensive and are slowly implementing more and more features of systemverilog that are synthesizable (and can be formally verified as well). But for FPGA it is different. The tools from the vendors (quartus, vivado) have paid as well as free versions. But they are nowhere near as expensive as ASIC tools. So, they lag behind in supported synthesizable systemverilog constructs. Xilinx and Intel (Altera) have tickets on their websites on several versions of their software with a list of unsupported systemverilog constructs. VHDL or verilog? It depends on your needs. And your budget. The expertise you need. Can you find employees that master that particular HDL language? It is all very dependant on your project, your team and your background.

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Which HDL language is used most?

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