ASIC and FPGA are quite hot today. Digital circuits design has evolved over the past few decades. Today we use a hardware description language or HDL to describe the hardware in a file. A synthesis tool translates the HDL source code in a digital circuit that uses the cells of the technology you target. But which technology is the most appropriate for our use case? Do we make an ASIC? Do we use an FPGA?
In theory, a HDL is an abstraction of the underlying technology. This means, we target the technology that we want and the EDA tools take care of that. As usual, there are very specific issues that need to be addressed by directly using technology cells in the HDL source code. The code is not portable anymore. Every time you target an FPGA or an ASIC technology, the specific cells are the problem. In case we target an ASIC process, let’s say 16nm TSMC, then we always prototype the ASIC in FPGA. We want to see parts or the whole design perform as close to real-time as possible. And the software team uses it to run and debug their code.
ASIC or FPGA?
A business case for a digital design needs to account for the price of the chip itself. An ASIC is not off-the-shelve, it is a specific design that has a cost upfront. NRE or non-recurring engineering cost is making an ASIC expensive. Usually, we choose ASIC when we plan on selling millions of chips. If the volume is lower, hundreds maybe a thousand, the cost for ASIC is too high. The business case benefits from using an off-the-shelve component. The FPGA is an ASIC but without the design cost. The FPGA tools convert the HDL into the cells and the routing that the FPGA needs. The benefit is that changes to the design are possible. You reconfigure the FPGA with that design and, there you are. It requires design and verification effort, but the cost is low compared to an ASIC budget.
Interesting read: What is the difference between FPGA, ASIC and PSoC?