Verilog was first, it has behavioural capabilities. Then came systemverilog with more advanced features, both RTL and behavioural. Important to note is that EDA tools support a subset of systemverilog. Especially for FPGA tools, there is limited systemverilog support. ASIC tools support more but they tend to cost (ten) thousands of dollars. Especially for verification systemverilog has excellent features.
What are the differences between verilog and systemverilog?