The two look similar, no doubt about it. But they are fundamentally different. VHDL is deterministic and strongly typed, verilog is not. Not a value judgement, just observation. Determinism is delta cycle convergence in VHDL. It requires you know how signals are routed, especially clocks. Delta cycle issues are a pain to solve, so avoid them by using the right methodology. Verilog has less strict types but has more flexibility. Eepecially for testbenches, probing, forcing, systemverilog was more innovative than VHDL. Every language has its plus and minus, usually it becomes a religuous war but I use both. Whatever the customer wants.
What are VHDL tips and tricks for designers with knowledge of verilog?