The trend is towards systemverilog for everything since both testbenches and RTL code can be written in the same HDL language, no need for mixed language licenses anymore. Of course legacy code and other factors require the companies to buy mixed language licenses but in theory systemverilog has everything to simulate and design. ASIC EDA tools are expensive and are slowly implementing more and more features of systemverilog that are synthesizable (and can be formally verified as well). But for FPGA it is different. The tools from the vendors (quartus, vivado) have paid as well as free versions. But they are nowhere near as expensive as ASIC tools. So, they lag behind in supported synthesizable systemverilog constructs. Xilinx and Intel (Altera) have tickets on their websites on several versions of their software with a list of unsupported systemverilog constructs.
What do you choose between VHDL and Verilog for VLSI design?