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What is the best software for Verilog/VHDL simulation?

Two distinct seperate categories: FPGA and ASIC.

For FPGA, the tools (even the free version) come with a simulator. But it is not the same performance nor has the same capabilities as commercial simulators. For hobby projects and for FPGA design it might be good enough.

For ASIC design and some FPGA companies they choose and EDA vendor for their tools. The big three would be Mentor (now Siemens), Cadence and Synopsys. For ASIC companies, an EDA vendor wants to sell the whole tool chain and hence you get the tools (simulator included) from one vendor since that will be the cheapest solution. Picking the best synthesis from A, the simulator from B and the backend from C, will cost (a lot) more money. There are differences between simulators in stability (bugs, crashes), RTL speed and gatelevel speed but thatis subject to change, development of those tools never stops. And designers have preferences sometimes but that is usually based on the simulator they are used to. A commercial company that needs to buy a simulator from an EDA vendor, could simply use an existing design and compare the EDA vendors tools with an evaluation license.

For verilog there is also a completely free simulator and also for VHDL there is one.

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