A digital VLSI engineer starts his or her career usually as a verification resource. Verification exposes you to the HDL language. Hardware description languages like VHDL and verilog. The difference in syntax between behavioural code and RTL implementations is important. Because, the designation “RTL” (register transfer level) means that the code can be translated by a synthesis tool into logic. That means digital logic, gates and flipflops. Behavioural code is not necessarily synthesizable. We use it for testbenches for example. So, it doesn’t need to be synthesizable. Hence a verification engineer uses the full syntax of the language. The design engineer needs to restrict himself or herself to the synthesizable subset of the language.
The verification engineer writes testbenches and runs simulations. A designer needs more experince with HDL’s, he understands the subset of the HDL that is synthesizable and knows the relationship between his code and the hardware. He can already foresee timing issues by coding accordingly, for example pipeline arithmetic algotihms. A designer needs a text editor, scripting experience, simulation experience and digital logic knowledge (including synthesis). A verification engineer needs a text editor, some scritping experience and use a simulator.
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