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What is the difference between floor planning in FPGA, Standard Cell Based Design (ASIC) and Gate Array?

I will oversimplify a bit. A gate array is mainly just a bunch of logic. An ASIC is a result of a netlist (logic gates, flops, and wires connecting them, produced by the frontend team), the layout team will take the netlist and based on the pinout, the location of the chip pins, will make a rough floorplan or placement of the hierarchy of the netlist.

Complexity

For multi-million gates ASIC designs, the tools can place any logic element on N locations, the next one on N-1 locations and so on. A bit oversimplified, but the tool has an impossible number of combinations to try out. Of course there are algorithms that bring more intelligence to the placement but in essence, a human is still the best initial floorplanner. If the tool has a good starting point it makes the tool’s life easier. The layout engineer places certain submodules of the design close to the IO pins. Then draw a shape of the surrounding modules. Suddenly, the tools have a good starting point and do a much faster and better job of doing the first placement. In principle, an ASIC has the most freedom for placement.

FPGA

An FPGA is actually an ASIC. An FPGA is configurable over and over again. It has a fixed layout with logic elements (different vendors have different terminology) but basically, there are just blocks with gates and flipflops in a group. That is the smallest logic block in an FPGA. Most of the time, there are also memory blocks (and dedicated DSP blocks) but we leave them out for simplification purposes. An FPGA is a kind of lego that you can interconnect (done by the tools) the way you need it.

The front-end design team runs the FPGA tools. Therefore, there is no separation between frontend and backend. And FPGA tools have leave less control to the user. The free version of the tools takes the IO pin positions and the logic netlist and tries to map it according to your constraints (timing and area). You can set the effort from small to medium to hard (latter is slowest). You can tweak a bit but you have almost no control on the floorplan, where the tool will place certain logic or submodules. In the paid version, there are ways of defining areas with a size and a coordinate to give the tool a precise area to use and lock it.

Conclusion

So, the FPGA designer is at the same time the place and route person too. With the paid version of the tools, a floorplan is possible. The designer locks parts of the design to certain areas. Small designs don’t need that.

For ASIC, there is a dedicated layout team with the required expertise to floorplan the ASIC. This is required to get a placement which matches the requirements fast. The experience of the layout person will define the time needed to get to a final placement that passes all checks, more experienced layout people will make a far better initial floorplan and get to a passing placement faster.

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