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What is the difference between structural and behavioural data flow modelling in Verilog?

Verilog has a syntax that can be used to describe and implement algorithms, testbenches, … You can use the full syntax. You can model a module cycle accurate or not cycle accurate. But the module is not (necessarily) synthesizable. It means that an EDA tool for synthesis is not able to convert the constructs used in what it knows, combinatorial logic and flipflops (simplification). Output logfiles or an input file with commands that is read in somewhere along the line of your simulation is not synthesizable per se. Hence there is a subset of verilog, the synthesizable subset, that the tools understand and support. An RTL designer uses this subset to describe the hardware of the design. Behavioural code is for modeling and testbenches. Structural modules are interconnect modules. I use this to have a toplevel above a few other modules. This toplevel is only wiring it has no logic in it. In synthesis this is an easy module, since you read in the db files of the submodules and you are done (except if you want to remove hierarchy or optimize unconnected stuff). There can be several sublevels of structural interconnect modules. It is called instantiation of modules, take there inputs and outputs and connect them up. Interconnect could be an internal connection or it can be a port of the interconnect module. Inference is not the same as instantiation. Instantiation is, you decide the module you instance. While, if you write “A+B”, the synthesis tool will choose an adder implementation, whatever matches the constraints you have imposed. You could also instantiate an adder that you implemented (or IP) by instantiating that adder module (and det dont touch) so that the synthesis tool has no choice for the adder implmentation. The benefit of inferring an adder is that you could target an ASIC technology or an FPGA with the same code.

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