Skip to content

What is the difference between Verilog and VHDL?

VHDL was developed by de DoD in the US as a hardware description language. Verilog is also a hardware description language. Digital logic design at the time was mostly hand designed, gates, flops and connect them all. Both languages are a layer on top of gates and flops. Similar to programming languages, if-then, case, for loops, … can be used and translated by a tool into a netlist. Netlists are always in verilog. VHDL is a strongly typed language, to force designers to use the right type for adders for example. An unsigned or a signed number are different. It also has range checks, if an integer is specified as 0 to 5, we know the hardware is actually 3 flops. There is nothing in HW that prevents the flops to be like the number 7. So, if you know 7 and 6 should never be in there, the simulator will give an out of range for this integer when, by mistake, the integer goes outside its boundary. Signals were requiring memory (attributes like lastvalue) and therefor variables were used, because a value gets overwritten immediately, speeding up simulation, needing less memory. When a signal triggers another signal, and that signalk triggers another signal, there is a need to come to a stable value in the simulation. Hence, VHDL uses the concept of zero time increments, delta cycles to come to a stable value of all signals in the design. If you have a race condition, there will not be a moment that the signals stop toggling because one signal triggers the other and the other then triggers the first one in the next delta cycle. If you understand delta cycles, your design should be taking this in account, for example, for feeding clocks and resets to your design. Verilog on the other hand, has no delta cycle mechanism. VHDL is deterministic, verilog is non-deterministic. Again, if you understand how verilog works, you take this into account. Verilog is not so strongly typed, it is closer to actual hardware and manual design. This means quicker simulation and netlists are always in verilog. Verilog is case sensitive, like C and C++. VHDL is not. Both have their benefits and drawbacks. But both look like programming languages but they are not. A C++ programmer could write great code but it will fail synthesis unless he knows about the relationship between HDL constructs and digital logic. They both have testbench capabilities, for verification which has evolved over the years. Systemverilog and UVM are very popular nowadays, because powerful verification with assertions, scorecards, … . I use both VHDL and verilog, but they are very different in doing almost the same thing, describing hardware. And, no ASIC designers do not prefer verilog. It is geography dependent and also linked to the company (big or small). I see all kinds because for a long time it was like religion to like one and trash the other. Systemverilog has now the upper hand. And I code in whatever HDL the client wants me to code.