VHDL was developed in the US by the defense department. I live in the EU and it was said that the EU would be mainly VHDL based and the US was verilog oriented. But nowadays, it is less strict to make that EU-US distinction. While both VHDL and verilog evolved over the years, systemverilog and UVM make it possible to use one language for design and verification. For EDA tool licenses this matters because having more than one HDL language requires more licenses which is more expensive. But this is the theory. Wihtin a company there is always legacy code, available in one language and reused. And if you have a large System on Chip (SoC), different IP providers offer different solutions and sometimes, the best match for what you want is not available in the HDL you want. The same for acquisitions which also bring in IP and designs in various HDL languages. So, the situation is still mixed HDL but I see a clear move toward systemverilog, away from VHDL. Some people like to trash verilog or VHDL but this is mostly because they lack in depth knowledge of the two, they are actually conceptually different. Especially in simulation, the boundary crossing from VHDL to verilog and from verilog to VHDL is a problematic area. If you understand both, you can take that into account upfront.. Conclusion? I see recruitment ads for Qualcom, Intel and others require both verilog and/or VHDL experience. Knowing the important conceptual differences makes you very valuable.