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At present, which language is mostly used by VLSI companies, Verilog or SystemVerilog for RTL or ASIC design?

Which HDL language fo you prefer? Well, one thing I have to make clear before I start my answer is that there are two HDL languages that are supported by most EDA tools. Verilog (and more and more constructs of systemverilog) and VHDL. First of all, they are not equal. Second, they both have their pro’s and con’s. I coded in both for a long time (two decades). So, that deep knowledge of both is needed to understand both. That is not the same thing as judging. Judging is for the youth, like the Stoics say, you start as a warrior, with age comes distance. The warrior becomes an observer.

HDL use in companies

In the ideal world, I would like to have one syntax, one HDL, open sourced with an open source parser supplied with every new version of the standard. Today EDA tool vendors charge for language neutral or single language licenses. If your design has two languages, you need two licenses. And these licenses don’t come cheap. It is a bit like the music industry, trying to defend their territory by locking in their vendor tools (the whole front-end and backend), keeping licenses inflexible (during a project verification demand goes up and down, sometimes half of the licenses are unused for weeks, later you are short on licenses). If the tools would be superb, without bugs (at least no crashes) and support would be swift to fix issues fast, then you could argue you get good quality for your money. This is not the case.

Congratulations: it’s a mix!

Normally the HDL language use is not really disclosed, maybe some semiconductor companies disclose it, but my experience is that it is more complicated than that. Some groups prefer one HDL over the other, maybe because they hired resources that are more experienced using one over the other. Legacy code is another thing. And IP vendors as well. Especially the smaller IP providers have their IP available in one HDL. I do see a lot more systemverilog today and less VHDL. See my answer a while ago:

What do you choose for VLSI design: VHDL or verilog?

Master both

As a self-employed digital VLSI designer, I am coding in both languages. The problem area is usually not the language itself, once you understand the concept and methodology, you can code RTL efficient in both. Also testbenches are quite adequate in both, with an advantage for systemverilog due to UVM (very important, UVM can have a negative impact as well, verification needs the right strategy and that is not always UVM). The problem is the boundary when crossing from VHDL to verilog and vice versa. This becomes clear after I explain the differences between the two.

What’s the difference between Verilog and VHDL?

For simulation, combining non-deterministic with deterministic is a problem that has no agreed-upon solution AFAIK. VCS assumes a one delta cycle delay when verilog signals go to the VHDL domain. But every vendor decides for himself how the boundary is implemented. That is why I think one language is the way to go whatever language that is. Just get rid of the problematic boundary issues.

Conclusion on your question: I have not seen verifiable numbers on “most-used” and “most-liked”. I think systemverilog has a good chance of domination but this will for sure make some VHDL warriors dig in. They will stick to VHDL and the whole environment and tools they have developed internally. As an observer, I just watch as it is happening now and in the future. May the best syntax win!

Published inASICPOST