Every ASIC designer starts with verification tasks. Verify functionality and learn about testbenches and automation (regression, self-checking). View a lot of RTL files and after a while also RTL design will be one of your skills. RTL and verification (behavioural) are all about a language (HDL) and EDA tools (simulators, compilers, …). But synthesis will link the HDL code to gates. So, an “If then” translates into a (priority) mux. A case statement will be an all-equal mux. Comparators, addition, substraction, multipliers, dividers, counters, … . DFT is again a step-up. Testmodes are there for functional (silicon) tests, to debug and for test (check if the chip is good after packaging or on the die itself). You need to know how a netlist (RTL translated by synthesis tool) looks like to stitch scan chains together, control all resets and clocks, … . Hence the level of experience and knowledge is much higher for DFT than for verification. Hence salary for DFT profiles will be higher than profiles that have only verification experience. They design, verify, know netlists, testmodes and generate test patterns.