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Why are initial blocks synthesizable in FPGA and not in ASIC?

We are describing hardware, this means logic gates )which have no memory and flipflops. Flops are memory elements that store a bit. They have a clock, the rhythm of change and a reset which brings them in a default state, binary 0 or 1. A hardware description language is describing hardware (duh) and the idea has always been to be independent of target tech and/or EDA vendor. An initial state as such is not real in hardware, it is a behavioral thing. In non-synthesizable code, it makes sense to assign an initial value to start with a known value, behavioral coding has no hardware equivalent. RTL code, the synthesizable code targets hardware.

FPGA reset

An FPGA powers up and uses the power on reset (POR) to bring the FPGA in a known state. This state is the configured state. The FPGA vendor decides if they support an initial value of the flops or not. But it goes against the agnostic HDL philosophy. If you ask an FPGA designer, they use initial statements is for not having a red undefined or “X” signal in the waveform viewer.

FPGA architecture is such that for maximum speed, the flops benefit from not having a reset at all. The state always needs a reset to a known state. Data does not, it holds temporary values anyway. For the flops that need a reset, the reset is synchronous. A long story to show the specific difference between ASIC design and FPGA design. An ASIC is just logic gates with wires. An FPGA boots into a configured state. The design configuration you designed.

ASIC reset

All ASIC flops need an asynchronous reset for DFT purposes (scan chains and test patterns). And an ASIC powers up but it is the ASIC designer that needs to bring the ASIC in a safe state. “Initial” has no meaning whatsoever in an ASIC. It knows only the safe state after the reset exit. Therefore, an ASIC has a clock and reset module which takes care of the safe state.

The power-on-reset (POR) is, for example, an RC network connecting to an input of the ASIC. The reset goes to the clock and reset module to distribute this reset to all flops in the design. In case of emergency, the whole chip can be reset, example a reset button that is an input to the ASIC. If the clock fails, there is no synchronous reset. An asynchronous reset always resets the chip into a safe state. An output that drives a pin is dangerous. In the reset state, the outputs are in high-impedance state. Even if another driver is on the bus, there is no damage to the chip. Safety first for ASIC design! Never allow initial statements in RTL code. I avoid it in the behavioral code as well.

Therefore, I always try to be independent of tools and tech and not use initial in HDL code.

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